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Mixed-Signal Design and Verification Engineer, Sr I

Synopsys

This is a Part-time position in Hamilton, ON posted April 28, 2021.

Job Description and Requirements Mixed-Signal Design and Verification Engineer Canada
– Ontario, Kanata In this role, you will contribute to the design of and verification of advanced high speed NRZ and PAM-4 SERDES IP in the latest FinFET technology nodes.

Besides taking responsibility for the architecture, design and implementation of full-custom blocks (e.g.

serializer, de-serializer, clock path), you will enforce a rigorous verification methodology of various full custom blocks.

You will generate digital models of analog blocks, representing functionality, timing and impairments.

With many analog blocks requiring digital correction to operate within specification, the co-verification of full custom logic and RTL will be essential.

Job responsibilities: Architect and implement full custom blocks such as serializer, de-serializer, clock path, etc.

Optimize the performance of high-speed mixed signal circuits by implementing and evaluating static timing analysis.

Deliver to the digital verification team accurate functional models of mixed-signal circuits.

Develop and maintain timing constraints for a STA flow on mixed signal circuits Deliver quality timing models of custom circuits to the place and route team.

Implement and verify digital calibration loops assisting mixed-signal circuits to meet performance targets.

Preferred Experience and Qualifications Demonstrated success in high speed SERDES (PCIE, Ethernet 28Gb/s and higher).

Demonstrated success in advanced CMOS (FinFET 16nm and below).

MSc or higher (preferred) with 5 years practical experience Expert level knowledge of the analog design flow (schematic entry, transistor level simulation, layout implementation).

Hands-on experience with high-speed, full-custom CMOS logic design and optimization.

Familiarity with the usage of the Verilog language applied in a full-custom design flow.

Knowledge of the modelling of clock jitter, signal frequency response and other impairments in a digital simulator simulation environment.

Familiarity with NanoTime and PrimeTime tools for static timing analysis (timing model generation (.lib)).

Hands-on experience with automated place-and-route tools is an asset.

Scripting skills and experience using languages such as Tcl, Python or Matlab.

Excellent communication and interpersonal skills.

Inclusion and Diversity are important to us.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canadasynopsys.com.